1. Field of Invention
The present invention relates to a wiring board and an electronic assembly, and more particularly, to a circuit board and an electronic assembly including a chip package and a circuit board.
2. Description of Related Art
In general, a conventional wiring board used for carrying and being electrically connected to a plurality of electronics includes a package substrate and a circuit board. The wiring board is constituted by alternately stacking a plurality of patterned conductive layers with a plurality of insulating layers. The patterned conductive layers are, for example, defined on a copper foil layer through a lithograph and etching process. The insulating layers are respectively disposed between the adjacent patterned conductive layers for isolating the patterned conductive layers. Moreover, the overlapping patterned conductive layers are electrically connected to each other through conductive vias.
As for the circuit board, a chip package can be disposed on its surface to form an electronic assembly. The chip package and the patterned conductive layer on the surface of the circuit board are electrically connected to each other, and electrical signal propagation can be achieved through the inner circuit of the circuit board.
FIG. 1A is a schematic top view of a conventional electronic assembly. FIG. 1B is a schematic cross-sectional view of FIG. 1A along the line A-A. Referring to FIGS. 1A and 1B, a conventional electronic assembly 100 includes a chip package 110 in a quad flat no-lead (QFN) package configuration (referred to QFN package for short hereafter), a circuit board 120, and a solder mask layer 130. The QFN package 110 includes a chip 112, a lead frame 114, a plurality of bonding wires 116, and an encapsulant 118. The chip 112 has an active surface 112a and a plurality of bonding pads 112b disposed on the active surface 112a. The lead frame 114 has a chip pad 114a and a plurality of inner leads 114b, wherein the chip 112 is disposed on the chip pad 114a. The chip pad 114a and the inner leads 114b are electrically connected to the bonding pads 112b via the bonding wires 116. The encapsulant 118 at least encapsulates the chip 112, the bonding wires 116, and a part of the lead frame 114.
The QFN package 110 is disposed on the circuit board 120. The circuit board 120 has two patterned conductive layers 122, an insulating layer 124, and a plurality of conductive vias 126. The insulating layer 124 is disposed between the two patterned conductive layers 122. The conductive vias 126 pass through the insulating layer 124 so as to electrically connect the two patterned conductive layers 122. As seen from FIGS. 1A and 1B, the patterned conductive layer 122 electrically connected to the QFN package 110 has a ground pad 122a and a plurality of signal lines 122b (only one signal line is shown in FIGS. 1A and 1B), such that the chip pad 114a of the QFN package 110 is disposed on the ground pad 122a, and one end of the signal line 122b is electrically connected to one of the inner leads 114b of the QFN package 110. Moreover, a solder mask layer 130 is disposed on the patterned conductive layer 122 electrically connected to the QFN package 110. The solder mask layer 130 has an opening 132 for exposing a part of the signal line 122b and the ground pad 122a. 
However, under high-frequency signal transmission, the induced inductance generated by the bonding wires 116 aggravates the impedance mismatch between the signal line 122b and the inner leads 114b electrically connected thereto; thus, the signal transmission quality between the signal line 122b and the inner leads 114b electrically connected thereto is thereby deteriorated.